The present invention relates to a semiconductor device, and more specifically, to a Flash device with twin-spacer floating gate and the structure of the same.
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the size reduction of a device. Thanks to their advantages, such as non-volatility, fast access time and low power dissipation, non-volatile memory can be applied as portable handy equipments, solid-state camera and PC cards. As known in the art, the nonvolatile memories are currently used in electronic devices to store structure data, program data and other data during repeated reading and writing operations. The field of the nonvolatile memories has recently focused on the electrically erasable programmable read only memory (EEPROM). The nonvolatile memories include various types of devices. One of the famous types is called EEPROM (electrically erasable programmable read only memory) Different types of devices have been developed for specific applications. These parts have been developed with a focus on the high endurance and high-speed requirements. EEPROM needs multi-layer of polysilicon and silicon dioxide, therefore, multi-masking are used during the fabrication, thereby increasing the time for manufacturing the devices. One of the present researches is focus on how to integrate the manufacture process to reduce the cost. One of the approaches is to integrate the memory process with the CMOS fabrication.
As known, a conventional EEPROM comprises a stacked gate including a floating gate used for storing charge, and a controlling gate which is used for controlling data storage. The floating gate is located between the control gate and the substrate without connecting to any bias line. The control gate connects to a word line. A source region and a drain region are coupled to a bit line. Memory arrays comprise a plurality of cells arranged on rows and columns, and each memory cell is identified by an own address and biases are coupled to the row and the column of the cell, so that the cell can be read and written. In general, the rows are known as word lines, and the columns are known as bit lines. Electrical connections are made with respect to each drain to enable separate accessing of each memory cell. Such interconnections are arranged in lines comprising the columns of the array. The sources in FLASH memory, however, are typically all interconnected and provided at one potential, for example ground, throughout the array. Accordingly, prior art techniques have been utilized to form a line of continuously running implanted source material within the semiconductor substrate and running parallel with the floating gate word lines. In a principal technique of achieving the same, the substrate has first been fabricated to form field oxide regions by LOCOS. The fabrication forms alternating strips of active area and LOCOS field oxide running substantially perpendicular to the floating gate word lines that will be subsequently formed. Thus running immediately adjacent and parallel with the respective word lines will be an alternating series of LOCOS isolation regions and active area regions on both the source and drain sides of a respective line of floating gates.
A prior art that relates to the field is disclosed in the U.S. Pat. No. 6,174,759 to Verhaar, entitled xe2x80x9cMethod of manufacturing a semiconductor devicexe2x80x9d. The assignee is U.S. Philips Corporation (New York, N.Y.) and filed the prior art on May 3, 1999. The method disclosed a process that can integrate with the CMOS process. Lucent Technologies, Inc. disclosed a single poly EEPROM on May 31, 2000 in U.S. Pat. No. 6,191,980. The device includes control device and erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell.
Taiwan Semiconductor Manufacturing Company disclosed a FLASH having spacer floating gate adjacent to the control gate in U.S. Pat. No. 6,228,695, entitled xe2x80x9cMethod to fabricate split-gate with self-aligned source and self-aligned floating gate to control gatexe2x80x9d, filed on May 27, 1999. A split-gate FLASH memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by depositing a poly-2 layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate FLASH memory cell.
Motorola, Inc. disclosed a FLASH device with spacer floating gate. Please turn to U.S. Pat. No. 5,494,838, entitled xe2x80x9cProcess of making EEPROM memory device having a sidewall spacer floating gate electrodexe2x80x9d. The article is filed on Feb. 27, 1996.
The object of the present invention is to disclose a nonvolatile memory with twin-spacer, wherein the twin spacer includes a conductive spacer floating gate and a conductive spacer control gate.
The further object of the present invention is to disclose a nonvolatile memory with a self-aligned control gate.
The steps of the present invention include forming the LOCOS for isolation. A pad oxide and a nitride layer are formed on the substrate. Subsequently, the nitride layer is next pattern on the substrate by using conventional lithography procedure. Successively, a polysilicon layer is formed along the surface of the nitride masking. The next step is to perform an anisotropically etch for etching the polysilicon layer, thereby forming conductive spacer lying on the sidewall of the opening of the nitride masking as the floating gate. A portion of the oxide layer is also removed to expose the substrate.
TEOS-oxide spacer is then formed on the conductive spacer by using conventional deposition and anisotropical etching. After the TEOS-oxide spacer is formed, a blanket ion implantation with n type conductive dopants such as arsenic and phosphorus are respectively doped into the substrate using the TEOS-oxide spacer as masking. Therefore, the n type highly doped source region is formed adjacent to the floating gate structures.
A further TEOS-oxide layer is formed on the nitride masking and the TEOS-oxide spacer, followed by etching the TEOS-oxide layer to remain the residual oxide on the top of the TEOS-oxide spacer. Next, the nitride masking and the pad oxide 6 are removed. In a preferred embodiment, the silicon nitride material may be removed by the using a heated solution of phosphorus acid. The silicon oxide layer may be removed by HF solution or BOE (buffer oxide etching) solution. A gate dielectric layer is then formed on the substrate after the removal of the nitride masking and pad oxide.
A dielectric layer is formed along the surface of the floating gates as a tunneling dielectric layer (or called inter-gate dielectric layer). Preferably, the tunneling dielectric may be composed by oxide, nitride, silicon oxynitride, ON (oxide/nitride) or ONO (oxide/nitride/oxide). A further conductive layer is formed on the tunneling dielectric layer as a control gate. Finally, an etching process is introduced to define the control gate and the control gate is self-aligned to the floating gate without the alignments procedure.
The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.